A floating-point division circuit executes an instruction for division by repeating a recursive procedure defined by the following equation. EQU R (j + 1) = r .times. R (j) - q.sub.j + 1 .times. D (1)
In the above equation, j represents an exponent of a recurrence formula and is either 0 or an integer in the range of 1 to n-1, D a divisor, q.sub.j + 1 a (j + 1)th quotient digit counting from a decimal point (q.sub.0 is a sign), n a digit length of a quotient, r a radix, r .times. R (j) a partial dividend before the (j + 1)th quotient digit is determined, R (j + 1) a partial remainder after the (j + 1)th quotient digit is determined, R (0) a dividend (initial value of the partial dividend), R (n) a final remainder.
The quotient Q is expressed by a series of (n + 1) quotient digits q.sub.0 - q.sub.n, as shown in the following equation. EQU Q = q.sub.0, q.sub.1, q.sub.2, . . . , q.sub.n - 1, q.sub.n( 2)
Accordingly, most of the time needed for an execution of a division is spent on a repetition of the above-mentioned recursive procedure. One approach to reduce the repetitions of this recursive procedure, so that division is speedily performed, is known as a non-recovery type division method. In this non-recovery type division method, attention is paid to the fact that a set of quotients used for generating a quotient digit q.sub.j + 1 could be a set of signed quotients not including 0, before selecting the quotient digit from the quotient set. Assuming that r is a radix, the above-mentioned set of signed quotients can be given by: EQU -0 (r - 1), - (r-2), . . . , -1, +1, . . . , r-2, r-1
This non-recovery type division method is characterized in that negative numbers are allowed to represent digits of the result of an operation by not recovering a reversal from positive to negative dividend, the reversal arising when determining each digit of the result of the operation; and that the divisor or a multiple of the divisor is added to or subtracted from the digit, depending on the sign of the dividend; the method is hence called a separation method.
In this method, a quotient is obtained by first placing, in a divisor register, a data for a multiple of the divisor that is k times the divisor (obtained by multiplying the divisor by each quotient of the above-mentioned set of signed quotients), selecting the above-mentioned divisor register on the basis of a prediction signal output from a quotient predicting device, and repeating addition or subtraction of the multiple of the divisor that is k times the divisor.
One variation of this non-recovery type division method, employed when a faster and more accurate division is to be performed, is known as a large-radix non-recovery division method that reduces the number of loops of division by increasing the radix r so that the number of bits that serve as an operation unit is relatively large.
A division circuit of this configuration can speed up an operation of a vector processor by having a division circuit running parallel with an addition circuit, a subtraction circuit, and a multiplication circuit. It should be noted, however, that addition, subtraction, multiplication, and division circuits do not receive an operation instruction all the time; there are times when they are not performing any operation. Electric power could be wasted because even when these circuits are at rest and performing no operations, merely inputting a clock signal thereto activates the circuits.
Accordingly, at a period of time when the addition, subtraction, multiplication, and division circuits are at rest and performing no operations, internal data in each circuit is maintained in a fixed status by omitting the latching of an input data by means of an input latch; power consumption is controlled by controlling the switching of transistors contained in each circuit.
In a division circuit employing a large-radix non-recovery type division method, the switching of transistors contained in the circuit cannot be controlled merely by fixing an input data by means of an input latch carried out in the absence of a division instruction, because the above-mentioned separation method is employed in this method in order to obtain a higher operation speed and is configured such that loops are executed internally. Thus, unlike the other circuits, the division circuit is not capable of keeping, even in the absence of a division instruction, the switching operations of the transistors therein from being performed due to an input clock, the switching operations being carried out just as when an instruction for division is input. Thus it is not only that power consumption cannot be controlled, power consumption even increases because the clock frequency therein is set at a high rate for speedy operation.
The present invention was developed in view of the above disadvantage and has an object of providing a floating-point division circuit in which the above disadvantage is eliminated by halting the operation of a quotient generating portion at least when no instruction for division is input.
Another object of the present invention is to provide a floating-point division circuit capable of outputting, when a pattern that is not of an arithmetic operation is detected during execution of an instruction for division, a prescribed pattern after halting an operation of a quotient generating portion.